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low skew, dual, 1-to-5, differential- to-2.5v, 3.3v lvpecl/ecl fanout buffer ics853210 idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 1 ics853210 rev a october 23, 2006 g eneral d escription the ics853210 is a low skew, high performance dual 1-to-5 differential-to-2.5v/3.3v lv pecl/ecl fanout buffer and a member of the hipercloc ks? f a m i l y o f h i g h p e r f o r mance clock solutions from idt. the ics853 210 is charac- terized to operate from either a 2.5v or a 3.3v power sup- ply. guaranteed output and part-to-part skew character- istics make the ics853210 ideal for those clock distribu- tion applications demanding well defined performance and repeatability. f eatures ? two differential 2.5v/3.3v lvpecl / ecl bank outputs ? two differential clock input pairs ? pclkx, npclkx pairs can accept the following differential input levels: lvpecl, lvds, cml, sstl ? maximum output frequency: >3ghz ? translates any single ended input signal to 3.3v lvpecl levels with resistor bias on npclkx input ? output skew: 13ps (typical) ? part-to-part skew: 85ps (typical) ? propagation delay: 485ps (typical) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -2.375v to -3.8v ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages b lock d iagram p in a ssignment hiperclocks? ic s 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ics853210 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 qa3 nqa3 qa4 nqa4 qb0 nqb0 qb1 nqb1 v cco qb2 nqb2 qb3 nqb3 qb4 nqb4 v cco v cco nqa2 qa2 nqa1 qa1 nqa0 qa0 v cco v cc nc pclka npclka v bb pclkb npclkb v ee pclka npclka qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 qa4 nqa4 pclkb npclkb qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 qb4 nqb4 v bb pulldown pullup/pulldown pulldown pullup/pulldown
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 2 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1v c c r e w o p. n i p y l p p u s e v i t i s o p 2c nd e s u n u. t c e n n o c o n 3a k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 4a k l c p nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 5v b b t u p t u o. e g a t l o v s a i b 6b k l c pt u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7b k l c p nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c c c . g n i t a o l f t f e l n e h w t l u a f e d 2 / 8v e e r e w o p. n i p y l p p u s e v i t a g e n 2 3 , 5 2 , 9v o c c r e w o p. s n i p y l p p u s t u p t u o 1 1 , 0 14 b q , 4 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 13 b q , 3 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 1 , 4 12 b q , 2 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 11 b q , 1 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 10 b q , 0 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 1 24 a q , 4 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 23 a q , 3 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 2 , 6 22 a q , 2 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9 2 , 8 21 a q , 1 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 3 , 0 30 a q , 0 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 5 7k ? r 2 / c c v s r o t s i s e r n w o d l l u p / p u l l u p 0 5k ? t able 3. c lock i nput f unction t able s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p r o a k l c p b k l c p r o a k l c p n b k l c p n , 4 a q : 0 a q 4 b q : 0 b q , 4 a q n : 0 a q n 4 b q n : 0 b q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " , n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 3 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v; v ee = 0v l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 23 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p 0 8a m t able 4b. lvpecl dc c haracteristics , v cc = 3.3v; v ee = 0v a bsolute m aximum r atings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc charac- teristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v cc 4.6v (lvpecl mode, v ee = 0) negative supply voltage, v ee -4.6v (ecl mode, v cc = 0) inputs, v i (lvpecl mode) -0.5v to v cc + 0.5v inputs, v i (ecl mode) 0.5v to v ee - 0.5v outputs, i o contin uous current 50ma surge current 100ma v bb sink/source, i bb 0.5ma operating temperature range, t a -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 47.9c/w (0 lfpm) (junction-to-ambient) l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 1 . 25 7 2 . 28 3 . 25 2 2 . 25 9 2 . 27 3 . 25 9 2 . 23 3 . 25 6 3 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 4 . 15 4 5 . 18 6 . 15 2 4 . 12 5 . 15 1 6 . 14 4 . 15 3 5 . 13 6 . 1v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 0 . 26 3 . 25 7 0 . 26 3 . 25 7 0 . 26 3 . 2v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 4 . 15 6 7 . 13 4 . 15 6 7 . 13 4 . 15 6 7 . 1v v b b 2 e t o n ; e c n e r e f e r e g a t l o v t u p t u o 6 8 . 18 9 . 16 8 . 18 9 . 16 8 . 18 9 . 1v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c 2 . 13 . 32 . 13 . 32 . 13 . 3v i h i t u p n i t n e r r u c h g i h 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l 1 k l c p , 0 k l c p 0 1 -0 1 - 0 1 - a 1 k l c p n , 0 k l c p n 0 5 1 -0 5 1 - 0 5 1 - a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . 1 k l c p n , 1 k l c p d n a 0 k l c p n , 0 k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n v s i c c . v 3 . 0 +
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 4 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer t able 4c. lvpecl dc c haracteristics , v cc = 2.5v; v ee = 0v t able 4d. ecl dc c haracteristics , v cc = 0v; v ee = -2.375 to -3.8v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 7 3 . 15 7 4 . 18 5 . 15 2 4 . 15 9 4 . 17 5 . 15 9 4 . 13 5 . 15 6 5 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 0 6 . 05 4 7 . 08 8 . 05 2 6 . 02 7 . 05 1 8 . 04 6 . 05 3 7 . 03 8 . 0v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 7 2 . 16 5 . 15 7 2 . 16 5 . 15 7 2 . 1 3 8 . 0 - v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 3 6 . 05 6 9 . 03 6 . 05 6 9 . 03 6 . 05 6 9 . 0v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 3 , 2 e t o n ; e g n a r e d o m n o m m o c 2 . 15 . 22 . 15 . 22 . 15 . 2v i h i t u p n i t n e r r u c h g i h 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l 1 k l c p , 0 k l c p 0 1 -0 1 -0 1 -a 1 k l c p n , 0 k l c p n 0 5 1 -0 5 1 -0 5 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o c c . v 2 - v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . 1 k l c p n , 1 k l c p d n a 0 k l c p n , 0 k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 3 e t o n v s i c c . v 3 . 0 + l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 5 2 1 . 1 -5 2 0 . 1 -2 9 . 0 -5 7 0 . 1 -5 0 0 . 1 -3 9 . 0 -5 0 0 . 1 -7 9 . 0 -5 3 9 . 0 -v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 9 8 . 1 -5 5 7 . 1 -2 6 . 1 -5 7 8 . 1 -8 7 . 1 -5 8 6 . 1 -6 8 . 1 -5 6 7 . 1 -7 6 . 1 -v v h i e g a t l o v h g i h t u p n i ) d e d n e - e l g n i s ( 5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -5 2 2 . 1 -4 9 . 0 -v v l i e g a t l o v w o l t u p n i ) d e d n e - e l g n i s ( 7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -7 8 . 1 -5 3 5 . 1 -v v b b 2 e t o n ; e c n e r e f e r e g a t l o v t u p t u o 4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -4 4 . 1 -2 3 . 1 -v v p p e g a t l o v t u p n i k a e p - o t - k a e p 0 5 10 0 80 0 2 10 5 10 0 80 0 2 10 5 10 0 80 0 2 1 m v v r m c e g a t l o v h g i h t u p n i 4 , 3 e t o n ; e g n a r e d o m n o m m o c v e e v 2 . 1 +0v e e v 2 . 1 +0v e e v 2 . 1 +0v i h i t u p n i t n e r r u c h g i h 1 k l c p , 0 k l c p 1 k l c p n , 0 k l c p n 0 5 10 5 10 5 1a i l i t u p n i t n e r r u c w o l 1 k l c p , 0 k l c p 0 1 -0 1 -0 1 -a 1 k l c p n , 0 k l c p n 0 5 1 -0 5 1 -0 5 1 -a v h t i w 1 : 1 y r a v s r e t e m a r a p t u p t u o d n a t u p n i c c v . e e . v 5 . 0 - o t v 5 2 9 . 0 + y r a v n a c 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n ? v o t o c c . v 2 - v . d e t i m i l s i n o i t a r e p o t u p n i d e d n e - e l g n i s : 2 e t o n c c . e d o m l c e p v l n i v 3 v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 3 e t o n h i . 1 k l c p n , 1 k l c p d n a 0 k l c p n , 0 k l c p r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e - e l g n i s r o f : 4 e t o n v s i c c . v 3 . 0 +
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 5 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer t able 5. ac c haracteristics , v cc = 0v; v ee = -2.375 to -3.8v or v cc = 2.375 to 3.8v; v ee = 0v l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m f x a m y c n e u q e r f t u p t u o3 >3 >3 >z h g p t h l 1 e t o n ; h g i h - o t - w o l , y a l e d n o i t a g a p o r p5 1 40 7 40 2 50 3 45 8 45 4 55 3 45 1 55 8 5s p p t l h , y a l e d n o i t a g a p o r p 1 e t o n ; w o l - o t - h g i h v 5 . 2 @0 0 40 7 40 4 55 2 40 9 40 5 55 4 45 1 55 8 5s p t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o3 15 23 15 23 15 2s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p5 80 6 15 80 6 15 80 6 1s p t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 25 1 18 8 10 6 20 3 10 9 10 5 25 4 10 9 15 3 2s p d e t s e t s r e t e m a r a p l l a . d e t o n e s i w r e h t o s s e l n u z h g 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o e h t t a d e r u s a e m s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 6 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer p arameter m easurement i nformation o utput l oad ac t est c ircuit d ifferential i nput l evel o utput s kew p art - to -p art s kew o utput r ise /f all t ime p ropagation d elay v cmr cross points v pp v ee v cc t sk(pp) t sk(o) nqx qx nqy qy pa r t 1 pa r t 2 nqx qx nqy qy clock outputs 20% 80% 80% 20% t r t f v swing t pd scope qx nqx lvpecl v ee 2v -0.375v to -1.8v v cc , v cco npclka, npclkb pclka, pclkb npclka, npclkb qa0:qa4, qb0:qb4, nqa0:nqa4, nqb0:nqb4, pclka, pclkb
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 7 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer a pplication i nformation figure 1a shows an example of the differential input that can be wired to accept single ended levels. the reference voltage level v bb generated from the device is connected to the negative w iring the d ifferential i nput to a ccept s ingle e nded lvpecl l evels f igure 1a. s ingle e nded lvpecl s ignal d riving d ifferential i nput input. the c1 capacitor should be located as close as possible to the input pin. vcc(or vdd) clk_in pclk npclk vbb figure 1b shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref ~ v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1b. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. vcc r2 1k v_ref c1 0.1u r1 1k single ended clock input pclk npclk
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 8 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer lvpecl c lock i nput i nterface the pclk /npclk accepts lv pecl, cml, sstl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the hiperclocks pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. f igure 2a. h i p er c lock s pclk/ n pclk i nput d riven by a cml d river f igure 2b. h i p er c lock s pclk/ n pclk i nput d riven by an sstl d river f igure 2c. h i p er c lock s pclk/ n pclk i nput d riven by a 3.3v lvpecl d river f igure 2d. h i p er c lock s pclk/ n pclk i nput d riven by a 3.3v lvds d river hiperclocks pclk npclk pclk/npclk 3.3v r2 50 r1 50 3.3v zo = 50 ohm cml 3.3v zo = 50 ohm pclk/npclk 2.5v zo = 60 ohm sstl hiperclocks pclk npclk r2 120 3.3v r3 120 zo = 60 ohm r1 120 r4 120 2.5v zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v f igure 2e. h i p er c lock s pclk/ n pclk i nput d riven by a 3.3v lvpecl d river with ac c ouple 3.3v r5 100 - 200 3.3v 3.3v hiperclocks pclk npclk r1 125 pclk/npclk r2 125 r3 84 c1 c2 zo = 50 ohm r4 84 zo = 50 ohm r6 100 - 200 3.3v lvpecl c2 r2 1k r5 100 zo = 50 ohm 3.3v 3.3v c1 r3 1k lvds r4 1k hiperclocks pclk npclk r1 1k zo = 50 ohm 3.3v pclk/npclk
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 9 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal dis- tortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board design- ers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for 3.3v lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination i nputs : pclk/npclk i nput : for applications not requiring the use of a differential input, both the pclk and npclk pins can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. r ecommendations for u nused i nput and o utput p ins o utputs : lvpecl o utput all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 10 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer t ermination for 2.5v lvpecl o utput figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. f igure 4c. 2.5v lvpecl t ermination e xample r2 50 zo = 50 ohm vcco=2.5v r1 50 zo = 50 ohm + - 2.5v 2,5v lvpecl driv er f igure 4b. 2.5v lvpecl d river t ermination e xample vcco=2.5v r1 50 r2 50 zo = 50 ohm r3 18 2,5v lvpecl driv er zo = 50 ohm + - 2.5v f igure 4a. 2.5v lvpecl d river t ermination e xample r2 62.5 2.5v 2,5v lvpecl driv er r3 250 zo = 50 ohm zo = 50 ohm r4 62.5 2.5v + - r1 250 vcco=2.5v
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 11 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics853210. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics853210 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 80ma = 304mw ? power (outputs) max = 30.94mw/loaded output pair if all outputs are loaded, the total power is 10 * 30.94mw = 309.4mw total power _max (3.465v, with all outputs switching) = 304mw + 309.4mw = 613.4mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.613w * 42.1c/w = 110.8c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 32- pin lqfp f orced c onvection
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 12 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco - 2v. for logic high, v out = v oh_max = v cco_max ? 0.935v (v cco_max - v oh_max ) = 0.935v for logic low, v out = v ol_max = v cco_max ? 1.67v (v cco_max - v ol_max ) = 1.67v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.935v)/50 ? ] * 0.935v = 19.92mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.67v)/50 ? ] * 1.67v = 11.2mw total power dissipation per output pair = pd_h + pd_l = 30.94mw f igure 5. lvpecl d river c ircuit and t ermination vcco - 2v q1 vout rl 50 vcco
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 13 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer r eliability i nformation t ransistor c ount the transistor count for ics853210 is: 437 pin compatible with mc100ep210 and mc100lvep210 t able 7. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 14 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer p ackage o utline and d imensions - y s uffix for 32 l ead lqfp n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0 t able 8. p ackage d imensions reference document: jedec publication 95, ms-026
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 15 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer t able 9. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t y a 0 1 2 3 5 8 s c iy a 0 1 2 3 5 8 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t y a 0 1 2 3 5 8 s c iy a 0 1 2 3 5 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l y a 0 1 2 3 5 8 s c il y a 0 1 2 3 5 8 s c ip f q l " e e r f - d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l y a 0 1 2 3 5 8 s c il y a 0 1 2 3 5 8 s c ip f q l " e e r f - d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o t i a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environmental r equirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
idt ? / ics ? 1-to-5, 2.5v, 3.3v lvpecl/ecl fanout buffer 16 ics853210 rev a october 23, 2006 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 8 t 1 9 5 1 . t e l l u b e e r f - d a e l d e d d a - n o i t c e s s e r u t a e f d e d d a . s n i p t u p t u o d n a t u p n i d e s u n u r o f s n o i t a d n e m m o c e r . e t o n d n a , g n i k r a m , r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 6 0 / 3 2 / 0 1
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ics853210 low skew, dual, 1-to-5, differential-to-2.5, 3.3v lvpecl/ecl fanout buffer ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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